Hereditary and sporadic beta-amyloidoses.

Cerebral amyloidoses are chronic, progressive neurodegenerative diseases that are caused by the aggregation and deposition of misfolded proteins in the central nervous system, and lead to cognitive deficits, stroke, and focal neurological dysfunction including cerebellar and extrapyramidal signs. Among them, beta-amyloidoses are a heterogenous set of conditions characterised by the deposition of beta-amyloid protein in brain parenchyma and/or vessel walls that lead to the development of two main clinico-pathological entities: Alzheimer's disease and cerebral amyloid angiopathy, which may be sporadic or familial, and may also co-exist in the same patient. The aim of this review is to describe the most important differences in the pathways leading to parenchymal and cerebrovascular beta-amyloidoses, and the main clinical, neuropathological and biochemical characteristics of the two conditions. It also discusses the phenotypes associated with a series of familial and sporadic beta-amyloidoses in more detail in order to highlight the clinical and neuropathological features that may help to distinguish the different forms of disease

Online Motion Planning for Safe Human–Robot Cooperation Using B-Splines and Hidden Markov Models

When humans and robots work together, ensuring safe cooperation must be a priority. This research aims to develop a novel real-time planning algorithm that can handle unpredictable human movements by both slowing down task execution and modifying the robot’s path based on the proximity of the human operator. To achieve this, an efficient method for updating the robot’s motion is developed using a two-fold control approach that combines B-splines and hidden Markov models. This allows the algorithm to adapt to a changing environment and avoid collisions. The proposed framework is thus validated using the Franka Emika Panda robot in a simple start–goal task. Our algorithm successfully avoids collision with the moving hand of an operator monitored by a fixed camera

Validation of landslide hazard assessment by means of GPS monitoring technique ? a case study in the Dolomites (Eastern Alps, Italy)

International audienceIn the last years a research project aimed at the assessment of the landslide hazard and susceptibility in the high Cordevole river basin (Eastern Dolomites, Italy) have been carried out. The hazard map was made adopting the Swiss Confederation semi-deterministic approach that takes into account parameters such as velocity, geometry and frequency of landslides. Usually these parameters are collected by means of geological and morphological surveys, historical archive researches, aerophotogrammetric analysis etc. In this framework however the dynamics of an instable slope can be difficult to determine. This work aims at illustrating some progress in landslide hazard assessment using a modified version of the Swiss Confederation semi-deterministic approach in which the values of some parameters have been refined in order to accomplish more reliable results in hazard assessment. A validation of the accuracy of these new values, using GPS and inclinometric measurements, has been carried out on a test site located inside the high Cordevole river basin

Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA

RISC-V is an open-source instruction set architecture (ISA) with a modular design consisting of a mandatory base part plus optional extensions. The RISC-V 32IMFC ISA configuration has been widely adopted for the design of new-generation, low-power processors. Motivated by the important energy savings that smaller-than-32-bit FP types have enabled in several application domains and related compute platforms, some recent studies have published encouraging early results for their adoption in RISC-V processors. In this paper we introduce a set of ISA extensions for RISC-V 32IMFC, supporting scalar and SIMD operations (fitting the 32-bit register size) for 8-bit and two 16-bit FP types. The proposed extensions are enabled by exposing the new FP types to the standard C/C++ type system and an implementation for the RISC-V GCC compiler is presented. As a further, novel contribution, we extensively characterize the performance and energy savings achievable with the proposed extensions. On average, experimental results show that their adoption provide benefits in terms of performance (1.64 7 speedup for 16-bit and 2.18 7 for 8-bit types) and energy consumption (30% saving for 16-bit and 50% for 8-bit types). We also illustrate an approach based on automatic precision tuning to make effective use of the new FP types

Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers

The analysis of source code through machine learning techniques is an increasingly explored research topic aiming at increasing smartness in the software toolchain to exploit modern architectures in the best possible way. In the case of low-power, parallel embedded architectures, this means finding the configuration, for instance in terms of the number of cores, leading to minimum energy consumption. Depending on the kernel to be executed, the energy optimal scaling configuration is not trivial. While recent work has focused on general-purpose systems to learn and predict the best execution target in terms of the execution time of a snippet of code or kernel (e.g. offload OpenCL kernel on multicore CPU or GPU), in this work we focus on static compile-time features to assess if they can be successfully used to predict the minimum energy configuration on PULP, an ultra-low-power architecture featuring an on-chip cluster of RISC-V processors. Experiments show that using machine learning models on the source code to select the best energy scaling configuration automatically is viable and has the potential to be used in the context of automatic system configuration for energy minimisation

A mixed-precision RISC-V processor for extreme-edge DNN inference

Low bit-width Quantized Neural Networks (QNNs) enable deployment of complex machine learning models on constrained devices such as microcontrollers (MCUs) by reducing their memory footprint. Fine-grained asymmetric quantization (i.e., different bit-widths assigned to weights and activations on a tensor-by-tensor basis) is a particularly interesting scheme to maximize accuracy under a tight memory constraint. However, the lack of sub-byte instruction set architecture (ISA) support in SoA microprocessors makes it hard to fully exploit this extreme quantization paradigm in embedded MCUs. Support for sub-byte and asymmetric QNNs would require many precision formats and an exorbitant amount of opcode space. In this work, we attack this problem with status-based SIMD instructions: rather than encoding precision explicitly, each operand's precision is set dynamically in a core status register. We propose a novel RISC-V ISA core MPIC (Mixed Precision Inference Core) based on the open-source RI5CY core. Our approach enables full support for mixed-precision QNN inference with 292 different combinations of operands at 16-, 8-, 4-and 2-bit precision, without adding any extra opcode or increasing the complexity of the decode stage. Our results show that MPIC improves both performance and energy efficiency by a factor of 1.1-4.9x when compared to software-based mixed-precision on RI5CY; with respect to commercially available Cortex-M4 and M7 microcontrollers, it delivers 3.6-11.7x better performance and 41-155x higher efficiency

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes

Heavily quantized fixed-point arithmetic is becoming a common approach to deploy Convolutional Neural Networks (CNNs) on limited-memory low-power IoT end-nodes. However, this trend is narrowed by the lack of support for low-bitwidth in the arithmetic units of state-of-the-art embedded Microcontrollers (MCUs). This work proposes a multi-precision arithmetic unit fully integrated into a RISC-V processor at the micro-architectural and ISA level to boost the efficiency of heavily Quantized Neural Network (QNN) inference on microcontroller-class cores. By extending the ISA with nibble (4-bit) and crumb (2-bit) SIMD instructions, we show near-linear speedup with respect to higher precision integer computation on the key kernels for QNN computation. Also, we propose a custom execution paradigm for SIMD sum-of-dot-product operations, which consists of fusing a dot product with a load operation, with an up to 1.64 × peak MAC/cycle improvement compared to a standard execution scenario. To further push the efficiency, we integrate the RISC-V extended core in a parallel cluster of 8 processors, with near-linear improvement with respect to a single core architecture. To evaluate the proposed extensions, we fully implement the cluster of processors in GF22FDX technology. QNN convolution kernels on a parallel cluster implementing the proposed extension run 6 × and 8 × faster when considering 4- and 2-bit data operands, respectively, compared to a baseline processing cluster only supporting 8-bit SIMD instructions. With a peak of 2.22 TOPs/s/W, the proposed solution achieves efficiency levels comparable with dedicated DNN inference accelerators and up to three orders of magnitude better than state-of-the-art ARM Cortex-M based microcontroller systems such as the low-end STM32L4 MCU and the high-end STM32H7 MCU

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

This paper presents Mr. Wolf, a parallel ultra-low power (PULP) system on chip (SoC) featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals. The small core can offload compute-intensive kernels to an eight-core floating-point capable of processing engine available on demand. The proposed SoC, implemented in a 40-nm LP CMOS technology, features a 108-mu W fully retentive memory (512 kB). The IO subsystem is capable of transferring up to 1.6 Gbit/s from external devices to the memory in less than 2.5 mW. The eight-core compute cluster achieves a peak performance of 850 million of 32-bit integer multiply and accumulate per second (MMAC/s) and 500 million of 32-bit floating-point multiply and accumulate per second (MFMAC/s) -1 GFlop/s-with an energy efficiency up to 15 MMAC/s/mW and 9 MFMAC/s/mW. These building blocks are supported by aggressive on-chip power conversion and management, enabling energy-proportional heterogeneous computing for always-on IoT end nodes improving performance by several orders of magnitude with respect to traditional single-core MCUs within a power envelope of 153 mW. We demonstrated the capabilities of the proposed SoC on a wide set of near-sensor processing kernels showing that Mr. Wolf can deliver performance up to 16.4 GOp/s with energy efficiency up to 274 MOp/s/mW on real-life applications, paving the way for always-on data analytics on high-bandwidth sensors at the edge of the Internet of Things

Semi-annual seasonal pattern of serum thyrotropin in adults

Circannual rhythmicity in thyroid-stimulating hormone (TSH) secretion is proposed, whereas evidences on seasonal peripheral thyroid hormones' fluctuation are contradictory. This study was designed to evaluate hypothalamic-pituitary-thyroid (HPT) seasonal secretion pattern using a big data approach. An observational, retrospective, big data trial was carried out, including all TSH measurements performed in a single laboratory between January 2010 and December 2017. A large dataset was created matching TSH data with patients' age, gender, environmental temperature exposure, and free triiodothyronine (fT3) and free thyroxine (fT4) when available. The trend and seasonal distributions were analysed using autoregressive integrated moving average models. A total of 1,506,495 data were included in the final database with patients mean age of 59.00 +/- 18.44 years. The mean TSH serum levels were 2.08 +/- 1.57 microIU/mL, showing a seasonal distribution with higher levels in summer and winter seasons, independently from age, gender and environmental temperatures. Neither fT3 nor fT4 showed a seasonal trend. TSH seasonal changes occurred independently from peripheral thyroid hormone variations, gender, age and environmental temperatures. Although seasonal TSH fluctuation could represent a residual ancestral mechanism to maintain HPT homeostasis, the underlying physiological mechanism remains unclear and specific studies are needed to clarify its impacting role in humans